A/D converters have the function of converting analog data output by a sensor or the like into digital data. For this reason, such an A/D converter functions as an interface between a physical phenomenon and a digital circuit. A/D converters are widely used in a variety of fields such as the communication, medical and measurement fields, and are applied to radio devices such as mobile phones and television sets, medical instruments, health instruments, and measuring instruments.
The use of a sigma-delta modulator as a component of an A/D converter is known from, for example, Japanese Unexamined Patent Publication No. 2006-333053. The A/D converter using the sigma-delta modulator is characterized by suppressing quantization error in such a way as to integrate the differentials between input signals and a quantization step using an integration circuit and continuously quantize them. Using such a sigma-delta modulator, a relatively high-resolution A/D converter can be implemented using a relatively small-chip area semiconductor integrated circuit.
FIG. 5 is a circuit diagram of one configuration of an A/D converter using a conventional sigma-delta modulator. The A/D converter shown in FIG. 5 includes a sigma-delta modulator 5 and a filter 9.
The sigma-delta modulator 5 integrates reference voltages +Vref and −Vref, whose polarities are controlled using a digital signal Ψ, and input voltages +Vin and −Vin, quantizes them, and then outputs a binary (or multinary) digital signal Ψ.
The filter 9 is a decimation filter or the like. The filter 9 performs processing, such as filtering or integrating, averaging and the like, on the digital signal Ψ output by the sigma-delta modulator 5, and outputs digital data corresponding to the input voltages +Vin and −Vin. The timing of switching between the reference voltages +Vref and −Vref is determined by the digital signal Ψ, as will be described later.
The sigma-delta modulator 5 includes an integration circuit 10, a first DAC unit 34, a second DAC unit 54, and a comparator 70.
The integration circuit 10 includes a fully differential amplifier 101, a first capacitor 107, a second capacitor 109, a first input resistor 103, and a second input resistor 105.
The fully differential amplifier 101 includes a non-inverted input terminal and an inverted input terminal as input terminals, and includes an inverted output terminal and a non-inverted output terminal as output terminals. Furthermore, the voltages at the inverted output terminal and non-inverted output terminal of the fully differential amplifier 101 are output to the comparator 70 as the results of the integration.
The first capacitor 107 connects the inverted output terminal and non-inverted input terminal of the fully differential amplifier 101 to each other, and feeds back the signal of the inverted output terminal to the non-inverted input terminal. Furthermore, the second capacitor 109 connects the non-inverted output terminal and inverted input terminal of the fully differential amplifier 101 to each other, and feeds back the signal of the non-inverted output terminal to the inverted input terminal.
The comparator 70 makes reference to a sampling clock not shown in the drawing, compares the two results of the integration output from the fully differential amplifier 101 in synchronization with the transmission timing of the sampling clock, and outputs the results of the comparison as a binary digital signal Ψ.
The first input resistor 103 includes one end configured such that the input voltage +Vin is supplied thereto and the other end connected to the non-inverted input terminal of the fully differential amplifier 101. Furthermore, the second input resistor 105 includes one end configured such that the input voltage −Vin is supplied thereto and the other end connected to the inverted input terminal of the fully differential amplifier 101.
The first DAC unit 34 includes a first switch 343, a second switch 345, and a first resistor 341. The reference voltage +Vref is supplied to one end of the first switch 343, and the other end of the first switch 343 is connected to one end of the first resistor 341. Furthermore, the reference voltage −Vref is supplied to one end of the second switch 345, and the other end of the second switch 345 is connected to one end of the first resistor 341. The first switch 343 switches between an ON state and an OFF state in response to the digital signal Ψ. Furthermore, the second switch 345 switches between an ON state and an OFF state in response to the inverted signal of the digital signal Ψ. The first switch 343 and the second switch 345 operate in a complementary manner thanks to the digital signal Ψ, and therefore the reference voltages +Vref and −Vref are fed back to the integration circuit 10 in response to the digital signal Ψ.
The second DAC unit 54 includes a third switch 543, a fourth switch 545, and a second resistor 541. The reference voltage −Vref is supplied to one end of the third switch 543, and the other end of the third switch 543 is connected to one end of the second resistor 541. Furthermore, the reference voltage +Vref is supplied to one end of the fourth switch 545, and the to other end of the fourth switch 545 is connected to one end of the second resistor 541. The third switch 543 switches between an ON state and an OFF state in response to the digital signal Ψ. Furthermore, the fourth switch 545 switches between an ON state and an OFF state in response to the inverted signal of the digital signal Ψ. The third switch 543 and the fourth switch 545 operate in a complementary manner thanks to the digital signal Ψ, and therefore the reference voltages +Vref and −Vref are fed back to the integration circuit 10 in response to the digital signal Ψ.